Newsgroup:
comp.cad.synthesis
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Question about "set_multicycle_path"
started 2003-10-29 03:58:39 UTC
2003-10-29 14:57:07 UTC
Ansgar Bambynek
1
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Low cost ASIC tools
started 2003-09-26 17:38:17 UTC
2003-10-13 20:26:59 UTC
Mike Stabenfeldt
3
replies
quick estimates of power and area for typical VLSI circuits
started 2003-09-12 08:54:44 UTC
2003-09-21 04:01:53 UTC
Uncle Noah
1
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quick estimates of power and area for typical VLSI circuits
started 2003-09-12 08:52:41 UTC
2003-09-13 02:42:33 UTC
Andrew Paule
1
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what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthesis simulation?
started 2003-09-07 20:30:30 UTC
2003-09-12 09:27:07 UTC
Chi
3
replies
No Transmission Gate in Standard Cell Library
started 2003-08-19 14:30:09 UTC
2003-09-10 21:45:48 UTC
B
1
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can anybody tell me why nanosim simulation gives out ZERO current?
started 2003-09-01 07:36:18 UTC
2003-09-03 18:28:16 UTC
B
1
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FS: NEW CAD/CAM/CAE soft.
started 2003-07-09 20:32:25 UTC
2003-08-10 09:58:45 UTC
mjmuir
1
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help link_library
started 2003-08-08 21:07:29 UTC
2003-08-09 09:19:16 UTC
Andy
2
replies
Ambit/PKS - Avoid synthesis of specific cells
started 2003-07-31 07:58:14 UTC
2003-08-09 04:40:34 UTC
Prasanna
4
replies
pls clarify my doubts
started 2003-07-29 20:45:43 UTC
2003-07-30 04:24:54 UTC
"Chris Zakrewsky" @ustation.se>
1
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EDIF file /netlist for FPGA
started 2003-07-19 03:03:47 UTC
2003-07-26 05:18:37 UTC
Ab Ran
1
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virtex2 libraries
started 2003-07-19 01:39:17 UTC
2003-07-23 21:56:47 UTC
Valdes
1
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synthesis of black box modules
started 2003-07-21 14:14:02 UTC
2003-07-21 20:50:41 UTC
Yardi
1
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Error using NClaunch vhdl tool
started 2003-07-09 06:08:45 UTC
2003-07-14 22:48:54 UTC
Ajeetha Kumari
1
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Help!Why I get all zero for area, timing and power in Synopsys Design Analyzer?
started 2003-06-30 08:33:27 UTC
2003-07-01 05:12:24 UTC
Jerry
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