Using a new standard cell library with Synopsys Design Analyzer

[Fazela]

Hi All,
I have a few VHDL designs which I want to synthesize using Synopsys DC
and write them out as structural verilog netlists. I also have a
standard cell library, the cells of which, I want use to actually
create the layout of the design.
For experimentation I used the library class.lib provided with the tool

to generate the netlist. But now so that the tool uses the gates and
cells available in the standard cell library, do I need to form a new
".lib" file and convert it into .db and provide it as the link library
and target library?
As a matter of fact, I tried doing this. I just replaced the names of
the cells in class.lib, with the names of the cells in the standard
cell library, the functionality remains the same. Then I used Library
Compiler to form the .db file and also changed the .synopsys_dc.setup
file to use this library before starting Design Analyzer. DA does not
give any errors in linking or compiling the design but it does not
write it out. I was wondering if there were other settings that need to

be done.

I would really appreciate your help.


Thanks,
FV

[Ashutosh]

Hi Fazela,

I tried, with success, using a new cell library with DC. However, I
did not (have to) use Library Compiler. What I needed was the same
library with double the area. Let the original library be in the file
a.lib and whose name (which appears in the header of a.lib) be
ORIG_LIB, and the new library be in the file b.lib whose library name
is NEW_LIB. I followed the following steps.

-> Copy a.lib into b.lib
-> Change b.lib in a text editor
- Change the area
- Change the library name from ORIG_LIB to NEW_LIB
-> read_lib b.lib into DC.
-> write_lib b.db NEW_LIB (meaning write the library NEW_LIB)
-> restart DC
-> Read the verilog
-> Modify the target library (which is b.db, also update search path)
-> Map

From your description, I can make a *guess* that the problem could be

because you have not changed the library name from ORIG_LIB to NEW_LIB.
Not doing so will mean you have two different libraries in two
different physical files (a.lib and b.lib) but when you read them in
DC, depending on the order, one of them will overwrite the previously
loaded library. If that happens (and assuming a.lib was loaded later),
the a.db and b.db will not be different.

regards,
Ashutosh