Newsgroup:
comp.cad.synthesis
Add New Display Options
1
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Persia Asynchronous Synthesis Tool
started 2008-02-05 21:10:52 UTC
2018-04-10 22:32:50 UTC
r***@gmail.com
2
replies
Calculate Delay from .Lib file
started 2006-08-29 04:46:24 UTC
2014-03-28 23:16:44 UTC
h***@gmail.com
1
reply
nanosim help
started 2008-12-17 18:27:49 UTC
2011-04-21 17:46:55 UTC
Jacklyn27COMBS
2
replies
Great service for books... Funded by libraries!
started 2009-04-04 04:29:00 UTC
2009-04-10 15:08:06 UTC
Linus Torwalds
1
reply
Find and fix critical path in gate level netlist by GOF.
started 2006-02-18 11:41:56 UTC
2009-04-06 08:57:24 UTC
nobody
5
replies
Breaking News ... Accellera Verification Working Group Forming
started 2008-04-25 22:35:49 UTC
2008-05-12 22:04:19 UTC
Dave Rich
1
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TSMC 90nm library spice deck
started 2007-11-05 22:34:51 UTC
2007-11-15 18:07:12 UTC
Colin Paul Gloster
12
replies
[ANNOUNCE] YARDstick - custom processor development toolset
started 2007-09-17 17:35:51 UTC
2007-09-21 06:26:09 UTC
Uncle Noah
1
reply
RTL Synthesis & SDF file
started 2007-08-30 02:01:34 UTC
2007-09-13 20:04:13 UTC
Koustav
2
replies
Question on .slib file extension
started 2007-09-04 22:40:27 UTC
2007-09-06 13:08:47 UTC
SB
1
reply
plib format
started 2007-08-26 05:34:39 UTC
2007-08-27 02:09:14 UTC
Alvin Andries
1
reply
A useful CPF (Common Power Format) website
started 2007-07-11 21:19:32 UTC
2007-08-04 01:26:24 UTC
g***@gmail.com
3
replies
Automatic Schematic Generation (System Graph) and Viewer
started 2007-07-19 09:17:41 UTC
2007-07-23 19:59:23 UTC
Shannon
1
reply
SynaptiCAD AllProducts, Synopsys, new programs,
started 2007-07-19 13:07:47 UTC
2007-07-20 16:52:12 UTC
Jogi
2
replies
gate sizing and interconnect delay
started 2007-06-06 08:22:54 UTC
2007-06-26 07:13:40 UTC
m***@gmail.com
4
replies
PrimePower
started 2007-06-17 19:15:32 UTC
2007-06-20 04:31:27 UTC
Alvin Andries
3
replies
Thomas & Moorby Verilog Reference: $41
started 2007-04-01 20:12:56 UTC
2007-04-03 19:09:17 UTC
hdl_book_seller
1
reply
[DC] Determine parameter in set_input_delay?
started 2007-02-26 14:32:49 UTC
2007-02-27 04:46:27 UTC
Alvin Andries
1
reply
a problem when using dc_shell-t>report_lib
started 2007-02-21 22:47:47 UTC
2007-02-26 04:02:26 UTC
Alvin Andries
1
reply
Datapath design problem?
started 2007-01-26 12:37:27 UTC
2007-01-29 04:37:02 UTC
Ray Andraka
5
replies
Use Multi-cycle Path or Pipeline?
started 2007-01-08 08:08:06 UTC
2007-01-08 21:30:07 UTC
Mike Treseler
9
replies
DC timing violation, what to do first?
started 2007-01-04 13:51:13 UTC
2007-01-06 02:48:55 UTC
Jim Lewis
1
reply
Should I use an external synthesis tool?
started 2006-11-06 22:15:20 UTC
2006-12-30 14:44:33 UTC
Gupta
1
reply
Verilog Ref Book
started 2006-11-26 22:46:24 UTC
2006-11-28 04:39:29 UTC
Guenter
2
replies
error help
started 2006-11-06 08:33:09 UTC
2006-11-15 06:38:40 UTC
p***@gmail.com
1
reply
creating a .lib file ?
started 2004-02-10 12:24:37 UTC
2006-11-10 00:31:04 UTC
pengdaimin
2
replies
generated clocks
started 2006-09-02 22:28:49 UTC
2006-09-03 13:34:52 UTC
arant
1
reply
Add money to your Paypal account with OPRAH V'vss
started 2006-08-16 06:26:53 UTC
2006-08-16 14:39:10 UTC
Jogi
1
reply
create_generated_clock (syntax, do I need it?)
started 2006-07-09 00:33:05 UTC
2006-08-01 03:38:32 UTC
a***@gmail.com
1
reply
Single bit wires instead of [0:0] busses?
started 2006-07-24 13:07:23 UTC
2006-07-26 22:26:46 UTC
Alvin Andries
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