r***@rogers.com
2006-07-08 19:32:59 UTC
Hi
I'm having an issue with create_generated_clock in design compiler. I
have a fast clock which I 1) invert and clock flops, 2) divide down and
use to clock more flops.
1) I invert the clock just by "assign clkInNot = ~clkIn;" inside a
module callded clkInv.
Q: Do I need to tell DC this is a clock or will it know?
2) I divide the clock inside a module called clkdiv:
clkdiv clkdiv_inst (
.clk_in(clk),
.clk_out(clk_divided),
);
and use the output to clock more flops. The create_generated_clock
statement looks like this:
create_generated_clock -name "DIV4_CLK" -divide_by 4 -source [get_port
"clk"] [get_pins "clkdiv/clk_out"]
However this clock does not appear in my clock report statements. Do I
have the syntax wrong?
Thanks.
I'm having an issue with create_generated_clock in design compiler. I
have a fast clock which I 1) invert and clock flops, 2) divide down and
use to clock more flops.
1) I invert the clock just by "assign clkInNot = ~clkIn;" inside a
module callded clkInv.
Q: Do I need to tell DC this is a clock or will it know?
2) I divide the clock inside a module called clkdiv:
clkdiv clkdiv_inst (
.clk_in(clk),
.clk_out(clk_divided),
);
and use the output to clock more flops. The create_generated_clock
statement looks like this:
create_generated_clock -name "DIV4_CLK" -divide_by 4 -source [get_port
"clk"] [get_pins "clkdiv/clk_out"]
However this clock does not appear in my clock report statements. Do I
have the syntax wrong?
Thanks.