Discussion:
Synthesis -> Physical Layout
(too old to reply)
KaRtiK
2004-01-30 21:11:36 UTC
Permalink
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

I want to compare layouts of different designs and study the tool(Cadence).
Thanks
Kartik
www.cae.wisc.edu/~kartik
Jerry
2004-01-31 01:16:20 UTC
Permalink
Post by KaRtiK
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the
tool(Cadence).
Post by KaRtiK
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII

Cherrs
Jer
Z
2004-02-06 19:20:52 UTC
Permalink
What tool set u have? Depending on that I can tell u how to do this.

-zk
Post by KaRtiK
Post by KaRtiK
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the
tool(Cadence).
Post by KaRtiK
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII
Cherrs
Jer
KaRtiK
2004-02-08 21:49:04 UTC
Permalink
Hello

I have the entire setup of Cadence,Synopsys,Xilinx and Mentor Graphics
tools in my Research lab.

I have synthesized my code using Design compiler.and wondering what
would be the design flow if I need to generate a layout a Cadence.

Thanks

Kartik

www.cae.wisc.edu/~kartik
Post by Z
What tool set u have? Depending on that I can tell u how to do this.
-zk
Post by Jerry
Post by KaRtiK
Hello
Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?
I want to compare layouts of different designs and study the
tool(Cadence).
Post by Jerry
Post by KaRtiK
Thanks
Kartik
www.cae.wisc.edu/~kartik
I thought Magma had a tool for this. RTL to GDSII
Cherrs
Jer
Eyck Jentzsch
2004-02-09 11:53:26 UTC
Permalink
Give SiliconEnsemble a try

-Eyck

Loading...