error help

[highbluff]

I have a clock constraint which goes like this.

create_generated_clock -name aclk -source [get_ports {bclk}] -divide_by
32 -duty_cycle 96 [get_ports {aclk}]

The Design compiler spits out an error message, which looks like this.
Error: Cannot specify -duty_cycle without -multiply_by. (UID-253)

Can someone please help.

[m***@gmail.com]

Just do what you are asked for: add switch "-multiply_by 1".

Post by highbluff
I have a clock constraint which goes like this.
create_generated_clock -name aclk -source [get_ports {bclk}] -divide_by
32 -duty_cycle 96 [get_ports {aclk}]
The Design compiler spits out an error message, which looks like this.
Error: Cannot specify -duty_cycle without -multiply_by. (UID-253)
Can someone please help.

[p***@gmail.com]

Post by highbluff
I have a clock constraint which goes like this.
create_generated_clock -name aclk -source [get_ports {bclk}] -divide_by
32 -duty_cycle 96 [get_ports {aclk}]
The Design compiler spits out an error message, which looks like this.
Error: Cannot specify -duty_cycle without -multiply_by. (UID-253)
Can someone please help.

You've probably figured this out by now, but create_generated_clocks
works on edges. On a divided clock, some edge of the master triggers
some edge of the slave. You can't have arbitrary duty cycles. The
default is to assume you want the edges set up so that the divided
clock has a 50/50 duty cycle. But you can change this using the -edges
switch. What you probably want is:

create_generated_clock ... -edges {1 31 32}. This gives a long high
time on a div 32 clock (rises on edge 1, falls on edge 31, rises again
on edge 32). For more details on -edges, see my paper at:

http://www.zimmerdesignservices.com/complex-clocking-situations-using-primetime.pdf

Parts of the paper are out of date (it's from 2001), but the section on
edges is still correct (around page 30).

The reason -duty_cycle exists is for MULTIPLY clocks. There's only one
edge involved, so PT needs to know when to toggle the clock.