ASIC RTL and FPGA RTL

[Anand P Paralkar]

Hi,

I was talking to an "expert" in synthesis and he mentioned that there is
a lot of difference between a synthesizable RTL code for a FPGA and a
synthesizable RTL code for an ASIC.

Is this true?

If so, could you please point the significant differences between the
two and what causes these differences.

Thanks,
Anand

[Alexander Gnusin]

Post by Anand P Paralkar
If so, could you please point the significant differences between the
two and what causes these differences.

You may be interested to read the recent article from eedesign.com:

http://www.eedesign.com/features/exclusive/showArticle.jhtml?articleId=18901725&kc=4235

Regards,
Alexander Gnusin