How can I calculate the gate count for a design?

[Lee]

Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.

Thanks

Adrian

[kal]

Post by Lee
Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.
Thanks
Adrian

You can do this by generating an area report (report_area -hier ).
This shows you the area of all blocks in some unit. This unit depends
on the cell library you used. To get the NAND2 count for the design,
you need to find out the size of the 1x drive NAND2 cell and divide
the total size to that number.

[Lee]

Hi,

What is the gate in "the gate count" mentioned by papers?NAND or NOR
or Inverter?

If I use the different basic gate, the gate count for a design could
be different. What is the usual way?

Thanks,

Adrian

Post by kal

Post by Lee
Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.
Thanks
Adrian

You can do this by generating an area report (report_area -hier ).
This shows you the area of all blocks in some unit. This unit depends
on the cell library you used. To get the NAND2 count for the design,
you need to find out the size of the 1x drive NAND2 cell and divide
the total size to that number.

[kal]

Post by Lee
Hi,
What is the gate in "the gate count" mentioned by papers?NAND or NOR
or Inverter?
If I use the different basic gate, the gate count for a design could
be different. What is the usual way?

The gate count is usually NAND2 with a 1x drive.