Infer dual-clock block RAM for Xilinx

[Amal]

Anyone has code templates for infering a dual-port, dual-clock, block
RAM (RAMB16) for Xilinix using Synplicity and VHDL?

Xilinx XST supports this using shared variable for memory and two
processes for each write port. But I can't seem to find anything for
Synplicity.

-- Amal

[John_H]

Have you tried to infer it yourself? It's something that's easy to do with
Synplicity's tools in Verilog, I imagine they do as good a job with VHDL.
You have an array, a write, and a read. You have your choice of a
registered read from a combinatorial address or an asynchronous read from a
registered address (which they translate back to the former, native
arrangement). They do a great job of taking care of the other control
signals as well.

The Synplify(Pro) online manual should also give you some guidance or at
least a description of what they expect to provide for support.

Post by Amal
Anyone has code templates for infering a dual-port, dual-clock, block
RAM (RAMB16) for Xilinix using Synplicity and VHDL?
Xilinx XST supports this using shared variable for memory and two
processes for each write port. But I can't seem to find anything for
Synplicity.
-- Amal