r***@rogers.com
2006-07-08 19:13:17 UTC
Hi,
Would someone look at the simplified code below and help me set the
timing constraints?
CODE:
output dataOut;
input clkIn;
input dataIn;
input TEST;
// Module which divides the clock by two
clkdiv clkdiv_inst (
.in(clkIn),
.out(clkIn_div_2).
);
// Latch data into two registers
always @ (posedge clkIn) begin
data_reg1 <= dataIn;
data_reg2 < = data_reg2;
end
// Output data at half the rate
always @ (posedge clkIn_div_2) begin
dataOut_reg <= {data_reg1, data_reg2};
// Mux between half rate and full rate
assign dataOut = (TEST) ? dataIn : dataOut_reg;
DESCRIPTION:
I latch in the data into two registers and output it at half the rate.
In test mode (TEST) I bypass the division by two and send the data
right out as is.
PROBLEM:
The data rate is very high (>1GHz) and I fail timig when in test mode.
HOWEVER in test mode I will be clocking my circuit a lot slower, so
this isn't an issue.
WHAT I WANT:
Tell design compiler to ignore the case when TEST==1.
Would someone look at the simplified code below and help me set the
timing constraints?
CODE:
output dataOut;
input clkIn;
input dataIn;
input TEST;
// Module which divides the clock by two
clkdiv clkdiv_inst (
.in(clkIn),
.out(clkIn_div_2).
);
// Latch data into two registers
always @ (posedge clkIn) begin
data_reg1 <= dataIn;
data_reg2 < = data_reg2;
end
// Output data at half the rate
always @ (posedge clkIn_div_2) begin
dataOut_reg <= {data_reg1, data_reg2};
// Mux between half rate and full rate
assign dataOut = (TEST) ? dataIn : dataOut_reg;
DESCRIPTION:
I latch in the data into two registers and output it at half the rate.
In test mode (TEST) I bypass the division by two and send the data
right out as is.
PROBLEM:
The data rate is very high (>1GHz) and I fail timig when in test mode.
HOWEVER in test mode I will be clocking my circuit a lot slower, so
this isn't an issue.
WHAT I WANT:
Tell design compiler to ignore the case when TEST==1.