synopsys parallel case

[Maryam]

Hi,
Would you mind please explain me the "synopsys parallel case " in
verilog.

Thanks a lot
Maryam

[m***@gmail.com]

I means that synopsys will build parallel logic for your mux.

[Maryam]

Thanks,
but please let me know it in details,what is the difference between the
synopsys parallel case and normal case?How and when we do use it?
If you can send me a link to read more about it I will be thankfull.

Maryam

[mk]

Post by Maryam
Thanks,
but please let me know it in details,what is the difference between the
synopsys parallel case and normal case?How and when we do use it?
If you can send me a link to read more about it I will be thankfull.
Maryam

Google is your friend: try
http://www.google.com/search?hl=en&q=parallel+case+verilog&btnG=Google+Search.
The first three links are pretty good.

[Michael Laajanen]

Hi,

Post by Maryam
Thanks,
but please let me know it in details,what is the difference between the
synopsys parallel case and normal case?How and when we do use it?
If you can send me a link to read more about it I will be thankfull.
Maryam

Without "synopsys parallel case" the case will be similar like a "if
then elsif elsif" statement.

/michael