Too big load in netlist after DC synthesis

[g***@yahoo.com]

After synthesizing my RTL code with Synopsys DC, I found that there are
so many gates which drive too many gates, and I have added the
"set_max_fanout 6 $current_design" in my TCL script. For example,
statements below in Verilog :
wire a;
wire [199:0] in_1, in_2;
reg [199:0] out;
if (a)
out = in_1;
else
out = in_2;
and ,the signal "a" will drive 200 signals in netlist. The result is
that the gate driving "a" drives too many signals and makes the gate
too big delay( there will be 4.5 ns in a NAND gate )

can someone tell me why?Thanks all

[m***@gmail.com]

It is understood why a is driving so many signals.
try:
set_max_fanout 6 [ current_design ]

Post by g***@yahoo.com
After synthesizing my RTL code with Synopsys DC, I found that there are
so many gates which drive too many gates, and I have added the
"set_max_fanout 6 $current_design" in my TCL script. For example,
wire a;
wire [199:0] in_1, in_2;
reg [199:0] out;
if (a)
out = in_1;
else
out = in_2;
and ,the signal "a" will drive 200 signals in netlist. The result is
that the gate driving "a" drives too many signals and makes the gate
too big delay( there will be 4.5 ns in a NAND gate )
can someone tell me why?Thanks all

[Aditya Ramachandran]

You can also try

set_max_fanout [all_designs]

I dont think that max_fanout is recursive so if a is in a submodule it
might not
work.

Aditya

Post by g***@yahoo.com
After synthesizing my RTL code with Synopsys DC, I found that there are
so many gates which drive too many gates, and I have added the
"set_max_fanout 6 $current_design" in my TCL script. For example,
wire a;
wire [199:0] in_1, in_2;
reg [199:0] out;
if (a)
out = in_1;
else
out = in_2;
and ,the signal "a" will drive 200 signals in netlist. The result is
that the gate driving "a" drives too many signals and makes the gate
too big delay( there will be 4.5 ns in a NAND gate )
can someone tell me why?Thanks all