help! how to resolve mismatches between pre- and post-synthesis simulation

[owl]

Hello,

As the subject. I'd like to know normally how you experts resolve the
mismatches. I'm more used to higher abstract level design, but now I'm
assigned a design with more than 100k gates and it resulted in tons of
mismatches between the pre- and post-synthesis simulations! If anybody
can give me some hint, like a link to a paper, book or website...
Thanks and bye,
Owl

[Paul Uiterlinden]

Post by owl
Hello,
As the subject.

What kind of mismatches are you talking about? If is is just differences
in propagation delay sampling the outputs with an appropriate clock
would solve that.

Mismatches can also be caused by differences in the initial state of
both implementations. Reset would help there.

If the mismatches are caused by difference in abstraction level, then
observing both designs on a higher level would be the way to go. A
testbench with some intelligence, giving a pass/fail indication would be
the best solution. This is the best solution anyway.

Paul.

[owl]

Hi,

Thanks a lot for Paul and Vikram. I'm sorry I haven't replied earlier.
Simply too busy with solving that problem. Finally my problem was
solved with the help of an engineer, who had done a similar design. In
the original RTL code, which we got as an IP core, they forget to reset
a few registers, which causes the protocol violations caught by an
self-test testbench.

However, my confusion is not gone. I know some mismatchs between pre-
and post-synthesis simulation, like certain delays, are reasonable.
Even glitches are understandable and most time (hopefully) harmless.
But, how can I know if a specific glitch/mismatch is harmless or not?
When you experts do the synthesis and find something going wrong,
you'll go for a coffee and then sit down, trying to solve the problem.
Then, the question is, how?

Best,
Owl

Post by Paul Uiterlinden

Post by owl
Hello,
As the subject.

What kind of mismatches are you talking about? If is is just

differences

Post by Paul Uiterlinden
in propagation delay sampling the outputs with an appropriate clock
would solve that.
Mismatches can also be caused by differences in the initial state of
both implementations. Reset would help there.
If the mismatches are caused by difference in abstraction level, then
observing both designs on a higher level would be the way to go. A
testbench with some intelligence, giving a pass/fail indication would be
the best solution. This is the best solution anyway.
Paul.

[Paul Uiterlinden]

Post by owl
Hi,
However, my confusion is not gone. I know some mismatchs between pre-
and post-synthesis simulation, like certain delays, are reasonable.
Even glitches are understandable and most time (hopefully) harmless.
But, how can I know if a specific glitch/mismatch is harmless or not?
When you experts do the synthesis and find something going wrong,
you'll go for a coffee and then sit down, trying to solve the problem.
Then, the question is, how?

The best way to check synthesis results is by Equivalence Checking (EC)
and Static Timing Analysis (STA). Both are static methods, which means
that no simulation is involved. That is a good thing, because coverage
by simulation heavily depends on the input vectors and observability of
the design. EC and STA are both formal methods, rigorously checking all
possibilities.

To come back on your original question: whether a different simulation
behavior is acceptable or not depends on whether it still matches the
requirements. In fact this is the same situation as when you assess the
RTL simulation results. Intelligent monitors (such as protocol checkers)
would help in this area.

Paul.

[Jason Zheng]

Post by owl
Hello,
As the subject. I'd like to know normally how you experts resolve the
mismatches. I'm more used to higher abstract level design, but now I'm
assigned a design with more than 100k gates and it resulted in tons of
mismatches between the pre- and post-synthesis simulations! If anybody
can give me some hint, like a link to a paper, book or website...
Thanks and bye,
Owl

see Cliff Cumming's paper on simulation/synthesis mismatch:
http://www.sunburst-design.com/papers/CummingsSNUG1999SJ_SynthMismatch_rev1_1.pdf

[VC]

Post by owl
Hello,
As the subject. I'd like to know normally how you experts resolve the
mismatches. I'm more used to higher abstract level design, but now I'm
assigned a design with more than 100k gates and it resulted in tons of
mismatches between the pre- and post-synthesis simulations! If anybody
can give me some hint, like a link to a paper, book or website...
Thanks and bye,
Owl

http://www.sunburst-design.com/papers/CummingsSNUG1999SJ_SynthMismatch_rev1_1.pdf

It may help to run a formal verification tool on the netlist and RTL.
If this results in a lot of mismatches, then try running on the
individual modules of the design and get them to pass and then move
onto the top level.

-Vikram.