PrimePower

[Koustav]

Hello everybody,

I wanted to a transient power analysis on
designs at cell/gate level. I have synthesized the netlist by cadence
buildgates. I was wondering if synopsis PrimePower could be used for
this. I do have the 90nm technology files (.tlf and .def).

Also since synopsis tools accept .lib format for
technolgy files, is there a way I could convert the .tlf into .lib
format?

Thanks,
Koustav

[Alvin Andries]

Post by Koustav
Hello everybody,
I wanted to a transient power analysis on
designs at cell/gate level. I have synthesized the netlist by cadence
buildgates. I was wondering if synopsis PrimePower could be used for
this. I do have the 90nm technology files (.tlf and .def).
Also since synopsis tools accept .lib format for
technolgy files, is there a way I could convert the .tlf into .lib
format?

Hi,

For a detailed power analysis, you'll need extracted parasitics to begin
with. This will allow you to do a gatelevel simulation with timing. Also,
power estimations of the gate will be more precise. As you've already
mentioned, PrimePower requires the .lib or .db (= compiled .lib) files for
your logic cells. The best source for these is your silicon vendor.

Regards,
Alvin.

[Koustav]

On Jun 18, 4:42 pm, "Alvin Andries"

Post by Alvin Andries

Post by Koustav
Hello everybody,
I wanted to a transient power analysis on
designs at cell/gate level. I have synthesized the netlist by cadence
buildgates. I was wondering if synopsis PrimePower could be used for
this. I do have the 90nm technology files (.tlf and .def).
Also since synopsis tools accept .lib format for
technolgy files, is there a way I could convert the .tlf into .lib
format?

Hi,
For a detailed power analysis, you'll need extracted parasitics to begin
with. This will allow you to do a gatelevel simulation with timing. Also,
power estimations of the gate will be more precise. As you've already
mentioned, PrimePower requires the .lib or .db (= compiled .lib) files for
your logic cells. The best source for these is your silicon vendor.
Regards,
Alvin.

Hello Alvin,

Thanks a lot for your advice. I was thinking of using
wire_load_models in my estimation
rather actual actual extractions of parasitic from the layout
(backannotating the vcd with sdf etc). I am targeting gate sizing on
the synthesized netlist and so dont want different routing decisions
to nullify my optimization.
and besides save a lot of time for PnR as well. What do you suggest?

Thanks,
Koustav

[Alvin Andries]

Post by Koustav
On Jun 18, 4:42 pm, "Alvin Andries"

Post by Alvin Andries

Post by Koustav
Hello everybody,
I wanted to a transient power analysis on
designs at cell/gate level. I have synthesized the netlist by cadence
buildgates. I was wondering if synopsis PrimePower could be used for
this. I do have the 90nm technology files (.tlf and .def).
Also since synopsis tools accept .lib format for
technolgy files, is there a way I could convert the .tlf into .lib
format?

Hi,
For a detailed power analysis, you'll need extracted parasitics to begin
with. This will allow you to do a gatelevel simulation with timing. Also,
power estimations of the gate will be more precise. As you've already
mentioned, PrimePower requires the .lib or .db (= compiled .lib) files for
your logic cells. The best source for these is your silicon vendor.
Regards,
Alvin.

Hello Alvin,
Thanks a lot for your advice. I was thinking of using
wire_load_models in my estimation
rather actual actual extractions of parasitic from the layout
(backannotating the vcd with sdf etc). I am targeting gate sizing on
the synthesized netlist and so dont want different routing decisions
to nullify my optimization.
and besides save a lot of time for PnR as well. What do you suggest?
Thanks,
Koustav

Hello,

Not using extracted parasitics means that you'll be way off for any
technology of 0.35um and smaller. With such a bad starting point, there's no
need to even start the exercise: you may make things worse.
I don't know the Cadence toos, but synopsys has some switches such that the
incremental synthesis would only do resizing. This would preserve your
routing.

So the proposed flow is:
o RTL -> gates
o gates -> placed gates (if going from RTL to placed gates with architecture
tradeoff is available, use it --> SNPS PC <= 2004.12, SNPS DC-t)
o power optimiziation 1 (create sensible simulation data first), this will
alter gates (and some clock gating if applicable) (use a quick route for
extracting parasitics or use global routing estimations generated by the
synthesis tool)
o CTS, route, scan insertion
o enable low leakage cells (if available) and power compile using resize
only (extracted
o hold fixing
o route cleanup
o timing sign-off

Alvin.

[brandon thompson]

Post by Koustav
Hello everybody,
I wanted to a transient power analysis on
designs at cell/gate level. I have synthesized the netlist by cadence
buildgates. I was wondering if synopsis PrimePower could be used for
this. I do have the 90nm technology files (.tlf and .def).
Also since synopsis tools accept .lib format for
technolgy files, is there a way I could convert the .tlf into .lib
format?
Thanks,
Koustav

Hi,

Along with doing the parasitic extraction, you will also want to run a
verilog simulator first (such as VCS, or whatever one you use). The
simulator can create a VCD file, which PrimePower uses as input so it
knows when all the switching events occur. With the design, the
parasitics, and the VCD file, you should be able to get PrimePower to
create power waveforms for the whole design and/or for subblocks and
cells you are interested in.

By the way, Synopsys has incorporated the PrimePower features into
PrimeTime, if you have the PrimeTime PX extension.

thanks,
brandon