Newsgroup:
comp.cad.synthesis
Add New Display Options
4
replies
Back Annotation simulations
started 2004-08-07 16:43:09 UTC
2004-08-10 12:57:27 UTC
Ansgar Bambynek
1
reply
Arnold Schwarzenegger Commits Suicide
started 2004-07-24 20:48:12 UTC
2004-07-25 00:58:07 UTC
kellnerp
3
replies
For Sale: Immersion Microscribe 3d digitizer
started 2004-07-18 01:07:23 UTC
2004-07-21 03:01:27 UTC
Sporkman
2
replies
Available: Open Source VHDL parser - for free
started 2004-07-13 04:36:58 UTC
2004-07-13 23:20:17 UTC
Phil Tomson
2
replies
Top Verilog & VHDL reference books at over 50% off
started 2004-07-07 03:32:59 UTC
2004-07-09 04:06:54 UTC
Jason Zheng
1
reply
dc_shell and synthesis using existing gates
started 2004-07-07 00:20:31 UTC
2004-07-07 06:20:30 UTC
kal
9
replies
parametric and feature based
started 2004-05-26 09:28:17 UTC
2004-06-02 10:20:58 UTC
Doug Dingus
7
replies
what is the meaning of CAE and CIM?
started 2004-05-14 14:28:38 UTC
2004-05-30 12:35:48 UTC
Doug Dingus
6
replies
scenario before parametric design concept..
started 2004-05-21 13:34:48 UTC
2004-05-25 04:20:19 UTC
Ben Loosli
9
replies
Simple way to generate random netlists of ALU cells
started 2004-05-14 11:00:33 UTC
2004-05-18 13:07:51 UTC
Fred Ma
1
reply
ASIC RTL and FPGA RTL
started 2004-04-26 10:58:40 UTC
2004-04-26 18:09:43 UTC
Alexander Gnusin
1
reply
error about synthesis and placement
started 2004-04-22 14:07:19 UTC
2004-04-23 09:30:56 UTC
kal
4
replies
Wire Load Models
started 2004-04-22 11:41:40 UTC
2004-04-23 09:28:25 UTC
kal
3
replies
When You Hear The Heavy Accent & The Poor Phone Connection... HANG UP!! ----- tK9BcMRYfVPe
started 2004-04-08 06:26:36 UTC
2004-04-09 02:53:11 UTC
Jeff Mowry
4
replies
Random logic verilog gate netlist generator
started 2004-02-14 09:53:33 UTC
2004-02-21 22:06:57 UTC
B. Joshua Rosen
3
replies
is it a library problem for synopsys and mentor?
started 2004-02-17 21:59:51 UTC
2004-02-20 16:39:38 UTC
Tracy
1
reply
!FOR SALE: CAD/CAM/CAE SOFTWARE <SOFTWARE SHOPPING>!
started 2004-02-09 03:59:49 UTC
2004-02-10 15:36:21 UTC
SOFTWARE SHOPPING
6
replies
SIS 1.3
started 2004-02-08 23:20:08 UTC
2004-02-09 22:49:56 UTC
Jack
4
replies
Synthesis -> Physical Layout
started 2004-01-31 03:11:36 UTC
2004-02-09 17:53:26 UTC
Eyck Jentzsch
1
reply
Q, SIS -1.2 linux installation guide
started 2004-02-07 21:47:19 UTC
2004-02-08 00:25:47 UTC
Phil Tomson
1
reply
Compile sis 1.2 on mac osx 10.3
started 2004-02-06 05:42:42 UTC
2004-02-07 13:57:07 UTC
Phil Tomson
38
replies
How Synopsys could save $$ without offshoring
started 2003-12-21 04:51:44 UTC
2004-02-05 02:36:25 UTC
fabbl
1
reply
Need SuperForge, AutoForge or Deform
started 2004-02-03 22:10:23 UTC
2004-02-04 04:03:17 UTC
TEL
3
replies
Synthesis errors?
started 2004-01-22 04:50:04 UTC
2004-01-22 18:54:15 UTC
John Adair
4
replies
Input Delay and Hold Time
started 2004-01-16 16:35:01 UTC
2004-01-20 21:59:16 UTC
Alexander Gnusin
2
replies
Free VHDL synthsis tools?
started 2004-01-11 03:31:18 UTC
2004-01-12 18:59:31 UTC
tbx135
1
reply
Please recommend me good books on IC Design / IC Design Process
started 2003-12-29 18:36:35 UTC
2003-12-30 20:47:57 UTC
tbx135
2
replies
Verilog-2001 `define expressions?
started 2003-12-06 13:07:58 UTC
2003-12-12 00:14:33 UTC
Hona
2
replies
goto statement is recommened in systemc?
started 2003-10-16 23:31:26 UTC
2003-11-18 21:47:50 UTC
David Pursley
3
replies
does anybody know how to use Nanosim with EDIF files?
started 2003-10-15 21:32:24 UTC
2003-11-12 15:36:52 UTC
Erik Wanta
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