Newsgroup:
comp.cad.synthesis
Add New Display Options
2
replies
help me
started 2006-07-11 18:36:13 UTC
2006-07-20 21:15:22 UTC
s***@gmail.com
4
replies
Design Compiler: Output mux for testing fails timing.
started 2006-07-09 00:13:22 UTC
2006-07-10 20:55:56 UTC
r***@rogers.com
3
replies
[synopsys] struggling
started 2006-06-19 16:24:47 UTC
2006-06-21 11:01:59 UTC
stefimke
1
reply
Synopsys Tetramax
started 2006-06-20 01:11:44 UTC
2006-06-20 12:36:12 UTC
m***@gmail.com
2
replies
Too big load in netlist after DC synthesis
started 2006-06-14 18:51:17 UTC
2006-06-15 14:36:43 UTC
Aditya Ramachandran
1
reply
Unsupported verilog construct with synopsys DC?
started 2006-06-15 03:30:47 UTC
2006-06-15 13:56:34 UTC
m***@gmail.com
1
reply
dc_shell and disabling datapath optimization variable
started 2006-05-20 12:37:51 UTC
2006-05-21 13:34:14 UTC
m***@gmail.com
1
reply
set_load & set_fanout_out
started 2006-05-18 06:38:35 UTC
2006-05-18 13:38:41 UTC
m***@gmail.com
1
reply
Define clock in Synplicity
started 2006-04-18 16:40:11 UTC
2006-05-16 18:42:32 UTC
g***@gmail.com
2
replies
Where can I find latency of my circuit in Synopsys Tools
started 2006-05-15 04:16:33 UTC
2006-05-16 05:37:54 UTC
SS
2
replies
Pros/Cons of skew & latency?
started 2006-04-13 16:12:46 UTC
2006-05-12 11:49:08 UTC
eda_cadence
1
reply
Verilog book recommendation
started 2006-04-29 07:12:11 UTC
2006-04-30 01:42:23 UTC
gabor
4
replies
synopsys parallel case
started 2006-04-16 09:24:45 UTC
2006-04-27 22:51:39 UTC
Michael Laajanen
4
replies
design compiler help
started 2006-04-11 01:43:06 UTC
2006-04-13 04:51:46 UTC
t***@gmail.com
1
reply
Nanosim with Synthesized Verilog
started 2006-04-11 13:49:00 UTC
2006-04-11 21:45:04 UTC
mk
1
reply
problem with post synthesis simulation with Scirocco using sdf file
started 2006-04-06 21:46:23 UTC
2006-04-10 11:49:14 UTC
battlefield2001
1
reply
Infer dual-clock block RAM for Xilinx
started 2006-04-07 20:50:43 UTC
2006-04-07 20:55:38 UTC
John_H
1
reply
Logic Depth Dependent Synthesis
started 2006-04-04 00:35:17 UTC
2006-04-07 03:32:01 UTC
David Wallace
4
replies
Urgent Help for xilinx Synthesizing
started 2006-03-16 22:31:08 UTC
2006-03-28 04:12:35 UTC
h***@yahoo.com
2
replies
Cell Layout View: Which Synopsys Tool?
started 2006-03-16 09:13:46 UTC
2006-03-27 23:35:50 UTC
h***@yahoo.com
1
reply
What happened to Synopsys Behavioral Compiler?
started 2006-03-06 06:11:28 UTC
2006-03-17 04:41:20 UTC
WEEB
2
replies
Some questions about Synopsys Physical Compiler..
started 2006-03-08 23:16:07 UTC
2006-03-09 15:16:44 UTC
m***@gmail.com
1
reply
From which memory-deep it is more meaningfully to use a RAM
started 2006-03-08 13:52:00 UTC
2006-03-08 15:25:20 UTC
m***@gmail.com
1
reply
Using a new standard cell library with Synopsys Design Analyzer
started 2006-02-16 02:37:30 UTC
2006-02-16 18:09:02 UTC
Ashutosh
1
reply
Latest CAD forums messages on your desktop
started 2005-12-26 03:34:30 UTC
2006-01-23 10:53:13 UTC
cadsxxx
5
replies
Close Timing and STA
started 2006-01-07 01:21:55 UTC
2006-01-09 14:57:43 UTC
n***@gmail.com
4
replies
How to judge a complete verification
started 2005-12-22 09:14:05 UTC
2005-12-23 10:23:30 UTC
n***@gmail.com
1
reply
problems when using Formality
started 2005-12-21 12:54:08 UTC
2005-12-21 22:38:56 UTC
n***@gmail.com
1
reply
Looking for free Formality guide
started 2005-12-19 23:35:56 UTC
2005-12-20 02:10:37 UTC
Alvin Andries
2
replies
LSI RAPIDCHIP
started 2005-10-17 05:57:11 UTC
2005-12-11 06:42:04 UTC
Jerry
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